1. Field of the Invention
The present invention relates generally to bonding materials for semiconductors, and more specifically to a compliant layer metallization for solder bonding a semiconductor.
2. Description of the Related Art
In many applications, it is necessary to bond semiconductors and/or semiconductor devices to a support or submount. This bonding is typically accomplished through the use of various types of solder (e.g., hard solder or soft solder). Semiconductors bonded in this way, however, frequently experience cracking due to thermal expansion mismatch and differences in mechanical strength between the semiconductor material and the submount material. Cracks of this nature have potentially significant reliability implications because they are not always screened out by electrical testing at the device level. In addition, because bonding related stress cracks frequently originate inside the bond joint, they are also often difficult or impossible to detect visually.
To alleviate this semiconductor cracking problem, use of a "compliant layer" between the semiconductor material and the submount is well known in the art. Ideally, a compliant layer used in this manner should provide both thermal (e.g., heat spreading) relief as well as mechanical (e.g., plastic) relief while at the same time promote ease of manufacturing of the semiconductor assembly. In addition, the compliant layer must also act as a barrier to protect the semiconductor from diffusion of soldering material into the semiconductor during manufacturing. The use of compliant layers to alleviate this semiconductor cracking problem has been attempted previously, however each such attempt has failed to meet at least one of the aforementioned requirements.
For example, the use of "thick layers" to provide heat spreading and mechanical relief is well known. These thick layers are typically composed of a single metal compatible with the soldering procedure, yet capable of providing mechanical and/or thermal relief. Such layers are formed by repeatedly plating the semiconductor with the single metal until the desired thickness is achieved. Typical plated single metal thick layers are in the 10-15 micron range.
The disadvantages associated with plated thick layers as employed in the art are numerous. First, the use of multiple plating operations to achieve a desired thickness is both time consuming and costly. This is especially true in light of the precautions which must be taken due to the presence of large amounts of toxic liquid (cyanide) which presents both an environmental risk and a potential health hazard to workers. In addition, despite multiple plating operations, only a "single metal" thick layer will result from such a plating operation. This means that the metal selected will, at best, represent a compromise selection chosen to provide thermal and mechanical relief while at the same time providing some barrier protection and manufacturability. Such a compromise selection, therefore, can not optimally address each compliant layer design concern.
The use of "barrier layers" to prevent diffusion of soldering material into a semiconductor is also well known. Like plated thick layers, the barrier layers in use are typically composed of a single metal, and are applied to the semiconductor via a plating process. Because only a single metal is involved, such barrier layers also represent a compromise selection and therefore fail to optimally address each of the compliant layer design concerns detailed above.
Therefore, there exists anteed for a compliant layer for use in bonding a semiconductor to a submount which can provide thermal and mechanical relief sufficient to prevent stress related cracking of the semiconductor, while at the same time provide barrier protection and promote ease of manufacturing. Such a compliant layer must optimally address each of these concerns, and ideally should be adaptable to any semiconductor-submount configuration. In addition, if such a compliant layer could be constructed solely of noble metals, it could be used as a wire-bondable surface to provide both solder-bondability and wire-bondability with a single process.